In U.S. Pat. No. 3,818,452 issued to D. L. Greer on June 18, 1974, a reprogrammable logic circuit array of the gated logic type was described. In that circuit, a two-dimensional orthogonal array of crosspoint logic cells contained at each crosspoint a gating element in the form of an IGFET (insulated gate field effect transistor) switching element in series with a programmable memory element in the form of a floating gate transistor. The array was capable of producing an output signal representing the Boolean function of several binary variable input logic signals. However, the array was programmed (written in) by means of avalanche breakdown induced by pulses of high voltage applied across the source and drain (high current carrying) terminals of selected floating gate transistors in the array; and there is no simple way of electrically erasing such an array. Therefore, the flexibility and usefulness of such a logic circuit array is rather limited. Moreover, the logic function access in that array is of the individually gated type, that is, where the binary ("1" or "0"; "true" or "false") logic signal variables are applied to the gate (low current carrying) terminals of the crosspoint IGFET gating elements in the array during computation. However, individually gated type logic arrays are more complex and require more space on the semiconductor chip than diode logic arrays (with a diode at each crosspoint instead of a transistor gate). Although the aforesaid Greer patent also disclosed programmable diode logic arrays, they were not reprogrammable at all. Accordingly, it would be desirable to have a logic circuit array which is electrically reprogrammable and which takes advantage of diode logic.